1. Field of the Invention
The present invention is related to radiation hardened integrated circuits and, more particularly, to clock generation circuits for radiation hardened integrated circuits.
2. Related Art
Increasingly, space-based communication systems are including integrated circuits (IC) made in advanced deep sub-micron Field Effect Transistor (FET) technology. Typically, these ICs are in the insulated gate silicon technology commonly referred to as complementary metal oxide semiconductor (CMOS). CMOS ICs are advantageous in that they are high speed and low power. The CMOS ICs use little power compared to what other technologies require for comparable speed and function.
In a space-based environment, however, ionic strikes by sub-atomic cosmic particles are known to introduce circuit disturbances. These circuit disturbances are known as single event effects (SEE) and, as single event upsets (SEU) when corrupting data in storage elements. Radiation hardened latches are well known and are used, effectively, to reduce or to eliminate SEU in space-based IC registers, latches and other storage elements. These radiation hardened storage elements are designed to protect from disturbance what is stored in them in spite of any cosmic particle hits that the storage elements might sustain.
However, over time, as circuit performance has increased, the propagation delay through the logic between the radiation hardened latches or registers has been reduced to within an order of magnitude of the duration of an SEE. For example, a pipelined logic chip operating at 200 MHz can have 3-3.5 nanoseconds allocated for logic propagation delays between registers. A single event upset occurring in the logic can cause an invalid result for 0.5-1.0 nanoseconds because this is a significant amount of time with respect to a pulse width. Such an event occurring in a clock distribution chain causes a more widespread and potentially a much more serious result.
Typically, chip clocks are received by a receiver connected to a bonding pad of the IC. The receiver buffers and redrives the clock, typically, to multiple locations on the chip. At each of these locations, the clock is again buffered and redriven. This rebuffered clock can further distributed to multiple locations, where it can again be rebuffered and redriven. The clock distribution can be represented as a tree spreading out from the original receiver.
The effects from an event occurring in a clock tree can cause a transient in the clock signal on part of the clock tree of approximately 0.5 nanoseconds, which can appear as a false clock pulse. Further, the number of latches and registers affected by the false clock pulse is random and depends on where in the tree the event occurs. Such a false clock pulse can clock registers causing the registers to latch invalid data. The invalid latched data can be passed from the initial registers through the next logic stage. This can result in multiple uncorrectable multi-bit logic errors.
The severity of this problem only increases with greater levels of very large scale integration (VLSI) circuit integration because these higher levels of integration achieve higher performance through smaller features. For example, with circuits operating in the 1 GHz clock range, a single event could wipe out an entire clock cycle for the affected part of the IC logic. Thus, it can be seen that clock tree SEE immunity is critical to preventing logic errors.
For example, FIG. 1 illustrates a typical state of the art scan d-flip-flop (scan dff) 100. The scan d flip-flop 100 includes a 2:1 multiplexer 102, which is coupled to a first level sensitive latch 104. The first level sensitive latch 104 is coupled to a second level sensitive latch 106. The scan dff 100 is clocked by a clock signal 107. The clock signal 107 is split into complementary signals by inverting clock signal 107 with inverter 108. The complementary clock signals are provided to first level sensitive latch 104 and second level sensitive latch 106, gating first and second pairs of pass gates 110, 112 and 114, 116, respectively.
When selected, an input DATAIN 118 passes through the 2:1 multiplexer 102 to the first pair of pass gates 110, 112 as complementary outputs 120, 122 of multiplexer 102. When the clock signal 107 is low, pass gates 110, 112, are turned on so that data and complementary outputs 120, 122 are passed to first level sensitive latch 104 and, tentatively, are stored therein. With the clock signal 107 low, the second pair of pass gates 114, 116 are contemporaneously turned off, and isolate the second level sensitive latch 106 from outputs 124, 126 of the first level sensitive latch 104.
The rising edge of clock signal 107 turns on the second pair of pass gates 114, 116 as the output of inverter 108 falls, simultaneously, to turn off the first pair of pass gates 110, 112. When the first pair of pass gates 110, 112 are turned off, the complementary outputs 120, 122 are isolated from the first level sensitive latch 104 and, so, data is latched in the first level sensitive 101 latch 104. When the second pair of pass gates 114, 116 are turned on, outputs 124, 126 of the first level sensitive latch 104 are passed to the second level sensitive latch 106. The state of outputs 124, 126, is stored, tentatively, in the second level sensitive latch 106 and, simultaneously, is passed out on an output DATAOUT 128. When clock signal 107 falls, on the next clock cycle, the second pair of pass gates 114, 116 are turned off, isolating the second level sensitive latch 106 from the outputs 104, 126 of first level sensitive latch 104, latching data in the second level sensitive latch 106 to complete the clock cycle.
Normally, when the clock signal 107 is well behaved with regularly spaced high and low periods, it is sufficient that data provided to the input DATAIN 118 meet setup (i.e., be valid for a specified period prior to the rise of clock signal 107) and hold (i.e., remain valid for a specified period after the rise of clock signal 107) timing requirements. At any time, other than this window around clock signal 107 rising, the state of input DATAIN 118 is specified as a xe2x80x9cdon""t carexe2x80x9d condition.
Unfortunately, an upsetting event occurring in the clock tree prior to clock signal 107 can cause a false clock pulse on clock signal 107. Since input DATAIN 118 is specified as a xe2x80x9cdon""t care,xe2x80x9d a falling edge of a false clock pulse on clock signal 107 could cause the first level sensitive latch 104 to switch states, inadvertently storing data. Further, when the input clock returns high, that invalid level can be passed to the second level sensitive latch 106 and out of the scan dff 100 on output DATAOUT 128. The false clock pulse is a pulse perturbated by an SEE.
Thus, for reasons stated above, and for other reasons stated below, which will become apparent to those skilled in the relevant art upon reading and understanding the present specification, what is needed are clock generation circuits with reduced SEE sensitivity.
The above mentioned problems with clock generation circuits and radiation hardened storage elements and other problems are addressed by the present invention and which will be understood by reading and studying the following specification.
In one embodiment of the present invention, a clock splitter circuit includes an event offset delay circuit, a first event blocking filter having inputs coupled to a delayed output and an undelayed output of the event offset delay circuit, and a second event blocking filter having inputs coupled to an inverted delayed output signal and an inverted undelayed output signal of the event offset delay circuit wherein the first event blocking filter has an output coupled to an input of the second event blocking filter and the second event blocking filter has an output coupled to an input of the first event blocking filter, a first clock driver having an input coupled to the output of the first event blocking filter and a second clock driver having an input coupled to the output of the second event blocking filter, and wherein the second clock driver has an input coupled to an intermediate output signal and the first clock driver has an input coupled to an inverted intermediate output signal of the event offset delay circuit for synchronization.
In one embodiment of the present invention, the event offset delay circuit can include first, second, third, fourth and fifth inverters coupled in series, where an input to the first inverter is the undelayed output signal and an output of the first inverter is the inverted undelayed output signal, where an input of the third inverter is the intermediate output signal, where an output of the third inverter is the inverted intermediate output signal, where an output of the fourth inverter is the delayed output signal, where an output of the fifth inverter is the inverted delayed output signal, where the undelayed output signal and the delayed output signal are coupled to the input of the first event blocking filter, and where the inverted undelayed output signal and the inverted delayed output signal are coupled to the input of the second event blocking filter.
In one embodiment of the present invention, the first event blocking filter includes three series coupled PFETs, a PFET coupled in parallel with a first and a second of the three series coupled PFETs, and four series coupled NFETs, a drain-source region of one of the four series coupled NFETs being coupled at a first in-phase output of the first event blocking filter to a drain-source region of a third of the series coupled PFETs, the source-drain region of the third one of the series coupled PFETs being a second in-phase output of the first event blocking filter.
In one embodiment of the present invention, a first of the three series coupled PFETs is gated by the delayed output signal and a second of the three series coupled PFETs is gated by the undelayed output signal.
In one embodiment of the present invention, a first of the four series coupled NFETs is gated by the undelayed output signal and a second of the four series coupled NFETs is gated to the delayed output signal, and the third NFET of the four series coupled NFETs is coupled to the output of the second event blocking filter.
In one embodiment of the present invention, a gate of the third of the three series coupled PFETs is coupled to ground.
In one embodiment of the present invention, the parallel coupled PFET is gated to an enable signal of the first event blocking filter.
In one embodiment of the present invention, the fourth NFET of the four series coupled NFETs is gated to the enable signal.
In one embodiment of the present invention, each of the first and the second clock drivers is an inverting clock driver and wherein the first clock driver includes, a first PFET having a source-drain region coupled to a supply voltage, and a gate of the first PFET gated by the first in-phase output of the first event blocking filter, a second PFET having a source-drain region coupled to a drain-source region of the first PFET, and a gate of the second PFET gated by an inverted intermediate output signal, and an NFET having a source-drain region coupled to ground, a gate of the NFET gated by the second in-phase output of the first event blocking filter, and a drain-source region of the NFET coupled to a drain-source region of the second PFET and a drain-source region of the NFET at an output of the first clock driver.
In another embodiment of the present invention, a clock splitter circuit is disclosed including a first event offset delay circuit and a second event offset delay circuit, a first event blocking filter having an input coupled to an input of the first event offset delay circuit, and having another input coupled to an output of the first event offset delay circuit, a second event blocking filter having an input coupled to an input of the second event offset delay circuit, and having another input coupled to an output of the second event offset delay circuit, a first synchronizer having an input coupled to an output of the first event blocking filter, and having another input coupled by a first pair of series coupled inverters to the output of the second event offset delay circuit, a second synchronizer having an input coupled to an output of the second event blocking filter, and having another input coupled by a second pair of series coupled inverters to the output of the first event offset delay circuit, a first clock driver having an input coupled to an output of the first synchronizer, and having another input coupled to an output of the second pair of series coupled inverters, and a second clock driver having an input coupled to an output of the second synchronizer, and having another input coupled to an output of the first pair of series coupled inverters.
In one embodiment of the present invention, the circuit further includes a first NOR gate and a second NOR gate receiving a clock signal and selectively providing the clock signal to one of the first and the second event offset delay circuits.
In one embodiment of the present invention, each of the first and the second event offset delay circuits includes three or more series coupled inverters.
In one embodiment of the present invention, the circuit further includes an inverter receiving an output of the first NOR gate and driving the input of the first event offset delay circuit from an output of the inverter, and a third pair of series coupled inverters receiving an output of the second NOR gate and driving the input of the second event offset delay circuit from an output of the third pair of series coupled inverters.
In one embodiment of the present invention, each of the first and the second event blocking filter includes two series coupled PFETs, and two series coupled NFETs, a drain-source region of one of the two series coupled NFETs being coupled at the output of the event blocking filter to the drain-source region of one of the two series coupled PFETs.
In one embodiment of the present invention, each of the first and the second clock drivers is an inverting clock driver and each of the clock drivers includes a PFET, having a source-drain region of the PFET coupled to a supply voltage, and a gate of the PFET gated by the input coupled to the synchronizer output, and an NFET, having a source-drain region of the NFET coupled to ground, a gate of the NFET gated by the output of the second pair of series coupled inverters, and a drain-source region of the PFET coupled to a drain-source region of the NFET at an output of the each of the clock drivers.
In one embodiment of the present invention, each of the first and the second clock drivers is an inverting clock driver and the first clock driver further includes an input coupled to the output of the first event offset delay circuit and the second clock driver further includes an input coupled to the output of the second offset delay circuit and each of the clock drivers includes, a first PFET, having a source-drain region coupled to a supply voltage, and a gate gated by the input coupled to the synchronizer output, a second PFET, having a source-drain region coupled to a drain-source region of the first PFET, and a gate gated by the coupled output of the event offset delay circuit, and an NFET having a source-drain region coupled to ground, a gate coupled to the output of the second pair of series coupled inverters, and a drain-source region coupled at an output of the each of the clock drivers to a drain-source region of the second PFET.
In yet another embodiment of the present invention, a clock splitter circuit for providing an SEU tolerant pair of non-overlapping complementary clocks is disclosed, where the clock splitter circuit includes a pair of cross-coupled clock buffers, each clock buffer including an event blocking filter of one of the pair of clock buffers receiving an undelayed clock signal and a delayed clock signal, the event blocking filter combining the undelayed clock signal with the delayed clock signal and an output of an event blocking filter of another of the pair of clock buffers, and providing at least one output, and a clock driver being driven by the at least one output to provide a clock phase output signal.
In one embodiment of the present invention, the circuit further includes at least one event offset delay circuit providing the delayed clock signal.
In one embodiment of the present invention, the event offset delay circuit includes a series of one or more inverters.
In one embodiment of the present invention, each clock driver is further driven by an intermediate clock signal to provide the clock phase output signal.
In one embodiment of the present invention, at least one event offset delay circuit is one event offset delay circuit and the series of inverters includes a series of 5 inverters providing an undelayed complementary undelayed clock signal pair, a delayed complementary clock signal pair and an intermediate clock signal pair.
In one embodiment of the present invention, the event blocking filter includes three series coupled devices of a first conduction type, four series coupled devices of a second conduction type, a conduction terminal of one of the three series coupled devices being coupled to a conduction terminal of the four series coupled devices, and a device of the first conduction type being coupled in parallel with two of the three series coupled devices.
In one embodiment of the present invention, the event blocking filter provides a pair of in-phase clock outputs, one of the pair of in-phase outputs is at a coupling point of the parallel coupled device and another of the pair of in-phase outputs is at the coupling point of the three series coupled devices with the four series coupled devices.
In one embodiment of the present invention, the devices of the first conduction type are P-type FETs and the devices of the second conduction type are N-type FETs, and the pair of in-phase outputs are separated by one of the three series coupled PFETs with a gate of the one of the three series coupled PFETs coupled to ground.
In one embodiment of the present invention, at least one event offset delay circuit is an event offset delay circuit in each the clock buffer, and wherein the event offset delay receives the undelayed clock signal and provides the delayed clock signal.
In one embodiment of the present invention, the event blocking filter includes two series coupled first conduction type devices coupled between a supply line and an output terminal, and two series coupled second conduction type devices coupled between said output terminal and a reference voltage line.
In one embodiment of the present invention, the first conduction type devices are P-type FETs and the second conduction type devices are N-type FETs.
In another embodiment of the present invention, a clock splitter circuit for providing an SEU tolerant pair of non-overlapping complementary clocks is disclosed, where the clock splitter circuit includes a pair of cross-coupled clock buffers, each clock buffer including event blocking means, of a first of the pair of clock buffers for blocking single event effects in a received clock signal, for combining the received clock signal with a complementary received output of another event blocking means for combining of a second of the pair of clock buffers, and for providing at least one output, and driver means for driving a non-overlapped clock responsive to the at least one output of the event blocking means.
In one embodiment of the present invention, the circuit further includes an event offset delay means for providing a delayed clock responsive to the received clock signal.
In one embodiment of the present invention, the driver means drives the clock further in response to a complementary intermediate clock signal.
In one embodiment of the present invention, a method of clocking an integrated circuit chip is disclosed including generating a first complementary pair of clock signals, generating a second complementary pair of clock signals, generating a first clock signal from an uninverted signal of the first complementary pair of clock signals and an uninverted signal of the second complementary pair of clock signals, generating a second clock signal from an inverted signal of the first complementary pair of clock signals and an inverted signal of the second complementary pair of clock signals, and synchronizing the first clock signal with the second clock signal.
In one embodiment of the present invention, a first latch clock and a second latch clock are non-overlapping clocks, and the method further includes generating the first latch clock from the first clock signal, and generating the second latch clock from the first clock signal, the first and the second latch clocks clocking the integrated circuit.
In one embodiment of the present invention, in the step of generating the first clock, a pair of in-phase clock signals is generated, and in the step of generating the second clock, a second pair of in-phase clock signals is generated.
In another embodiment of the present invention, a clock splitter circuit is disclosed, including a first synchronizer and a second synchronizer, a first clock driver having a first input coupled to an output of the first synchronizer, and a second input coupled to a first input of the second synchronizer, a second clock driver having a first input coupled to an output of the second synchronizer, and a second input coupled to a first input of the first synchronizer, a first inverter and a second inverter coupled in series, coupled at an output of the first inverter to a third input of the first clock driver, and coupled at an output of the second inverter to a second input of the first synchronizer, a third inverter having an input coupled to the output of the second inverter and having an output coupled to the second input of the first clock driver, a fourth inverter having an input coupled to a third input of the second clock driver, and a fifth inverter having an input coupled to an output of the fourth inverter, and having an output coupled to the first input of the second clock driver.
In one embodiment of the present invention, the circuit further includes a first NOR gate having a first clock input and a second clock input, and having an output coupled to the input of the first inverter, and a second NOR gate having a first clock input and a second clock input coupled to the second clock input of the first NOR gate, and having an output coupled to the input of the fourth inverter.
In an embodiment of the present invention, a clock splitter circuit is disclosed for providing a single event upset (SEU) and single event effect (SEE) tolerant clock signal. In one embodiment, the clock signals can be used to clock latches in a space-based environment. The clock splitter circuit can include in one embodiment one or more event offset delay circuits. The event offset delay circuit receives a clock signal and generates a delayed clock signal. The event offset delay circuit can generate an inverted clock signal, a delayed inverted clock signal and a pair of intermediate clock signals. The delayed clock signal and inverted delayed clock can be delayed by the known duration of single event effects (SEE). The delayed and undelayed clock signals can be passed to an event blocking filter which blocks any disturbance in the delayed and/or undelayed clock signal. A synchronizer can synchronize the event blocking filter output signals prior to, or coincident with, being passed to corresponding inverting clock drivers. The synchronizers also can insure that the synchronized blocking filter output signals can not be low simultaneously. Corresponding ones of the intermediate clock signals can also be provided to the inverting clock drivers. The inverting clock driver outputs can be a pair of SEU tolerant nonoverlapping clock phase signals for driving one or more latches.
It is an advantage of the invention that integrated circuit chip SEE sensitivity can be reduced.
It is another advantage of the invention that integrated circuit power can be reduced.
It is yet another advantage of the invention that integrated circuit chip clock tree SEE sensitivity can be reduced.
It is yet another advantage of the invention that timing related SEU sensitivity is reduced on space based integrated circuit chips.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digits in the corresponding reference number.